Surrounding Gate Transistor

But the planar scaling approach hit a limit due to the ‘short channel effect’ and increased leakage currents. The industry eventually transitioned towards the FinFET structure in the early 2010s.

The larger surface area between the gate and channel enables better performance and the vertical geometry of the FinFET reduced its footprint, allowing more transistors to be integrated into a chip.

A FinFET could have a single fin, or multiple fins arranged side-by-side, to increase drive strength and performance, at the expense of increased area.

Eventually, FinFET scaling hit various limitations, mostly related to the consequences of having the taller and narrower fins required to increase performance. This included increased leakage currents and short channel effects.

So, to improve control of the transistor channel, the industry decided to move from the FinFET towards the Gate All Around (GAA) transistor. This was first presented by Unisantis Electronics’ founding CTO, Dr. Masuoka, in 1988.

In a GAA transistor, the channel is surrounded on all four sides by the gate. A GAA can be constructed with either nanowire (tubular) or a nanosheet (flat and wide) channels. Planar nanosheet/nanowire channels can be stacked to increase the channel width.

In a nanowire, one has full control of the channel, by having the gate wrapping around a circular silicon channel, providing the best channel control.

The nanosheet structure is a compromise, being part-way between a FinFET and a nanowire. Its width is much larger than the nanowire. Gate electrostatic control is not as good as that of the nanowire, though it does have good drive current.

Nanowire GAAs are therefore better suited to ultra-low power applications, while nanosheet GAAs are suited to high-performance applications at the expense of power and area.

Recently introduced GAA FETs are implemented laterally, and like the FinFET, have limits to their scaling (gate length, spacer thickness and contact size).

And when transistors can’t be made any smaller, the only way to make progress is to go upwards.

This changes the layout configuration from 2D to 3D, with gate length defined vertically – ensuring that gate length can be more relaxed without consuming a larger area on the silicon wafer. It also allows the nanowire diameter to be relaxed while preserving short channel electrostatic control.

Relaxation in gate length allows for optimisations, for example, increasing the gate length can improve the performance and stability of SRAMs. Doing this on a lateral GAA would increase the cell’s footprint.

As part of its ongoing research, Unisantis Electronics created  SGT-based super-scaled SRAM bit cells. Using SGT they reduced 6T SRAM area by 20-30% compared with lateral nanowire GAA FETs. The SRAM cells, shown below, showed improved read and write stability, lower minimum operating voltages and lower standby leakage values.