2019 Symposium on VLSI Technology and Circuits, Kyoto Japan
12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices
VLSI2019_Ver-2.2VLSI 2019 Presentation – Unisantis / IMEC 🔗
VLSI-Presentation-Unisantis